// 假设已有 interface 定义： aru_ub_rdgen_cfg_if, ub_rd_req_if, aru_ub_dat_if, aru_payload_if

module tb_top;
    // clock / reset
    logic clk;
    logic rst_n;

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    initial begin
        rst_n = 0;
        #20 rst_n = 1;
    end

    // instantiate interface instances (需要传入 clk 和 rst_n)
    aru_mux_cfg_if u_aru_cfg_if_inst0 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_in_if_inst0 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out0_if_inst0 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out1_if_inst0 (
        .clk  (clk),
        .rst_n(rst_n)
    );

    aru_mux_cfg_if u_aru_cfg_if_inst1 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_in0_if_inst1 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_in1_if_inst1 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out_if_inst1 (
        .clk  (clk),
        .rst_n(rst_n)
    );

    aru_mux_cfg_if u_aru_cfg_if_inst2 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_in_if_inst2 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out0_if_inst2 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out1_if_inst2 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out2_if_inst2 (
        .clk  (clk),
        .rst_n(rst_n)
    );

    aru_mux_cfg_if u_aru_cfg_if_inst3 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_in_if_inst3 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out0_if_inst3 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out1_if_inst3 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out2_if_inst3 (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_payload_if u_pld_out3_if_inst3 (
        .clk  (clk),
        .rst_n(rst_n)
    );

    // DUT 实例化：把 interface instance 传进去（匹配 modport 类型）
    aru_mux_1_to_2 dut (
        .clk          (clk),
        .rst_n        (rst_n),
        .u_cfg_if     (u_aru_cfg_if_inst0),   // 连接接口实例
        .u_pld_in_if  (u_pld_in_if_inst0),
        .u_pld_out0_if(u_pld_out0_if_inst0),
        .u_pld_out1_if(u_pld_out1_if_inst0)
    );

    aru_mux_2_to_1 dut1 (
        .clk         (clk),
        .rst_n       (rst_n),
        .u_cfg_if    (u_aru_cfg_if_inst1),  // 连接接口实例
        .u_pld_in0_if(u_pld_in0_if_inst1),
        .u_pld_in1_if(u_pld_in1_if_inst1),
        .u_pld_out_if(u_pld_out_if_inst1)
    );

    aru_mux_1_to_3 dut2 (
        .clk          (clk),
        .rst_n        (rst_n),
        .u_cfg_if     (u_aru_cfg_if_inst2),   // 连接接口实例
        .u_pld_in_if  (u_pld_in_if_inst2),
        .u_pld_out0_if(u_pld_out0_if_inst2),
        .u_pld_out1_if(u_pld_out1_if_inst2),
        .u_pld_out2_if(u_pld_out2_if_inst2)
    );

    aru_mux_1_to_4 dut3 (
        .clk          (clk),
        .rst_n        (rst_n),
        .u_cfg_if     (u_aru_cfg_if_inst3),   // 连接接口实例
        .u_pld_in_if  (u_pld_in_if_inst3),
        .u_pld_out0_if(u_pld_out0_if_inst3),
        .u_pld_out1_if(u_pld_out1_if_inst3),
        .u_pld_out2_if(u_pld_out2_if_inst3),
        .u_pld_out3_if(u_pld_out3_if_inst3)
    );

    // （可选）在 tb 里驱动接口信号，或在接口内写 driver/monitor task/class
    initial begin
        #1000 $finish;
    end
endmodule
